By Alun Williams 17th March 2014
Today, designers face increasing project requirements for densely populated electronic circuits including pressures to reduce manufacturing times and costs, writes Ben Jordan of Altium, in the third of a three-part series. To meet these requirements, design teams have increasingly turned to 3D rigid-flex circuits to meet their project’s performance and production requirements. However, designing for flex or rigid-flex presents a number of challenges to electronic and mechanical design teams, that require careful consideration.
Today, designers face increasing project requirements for densely populated electronic circuits including pressures to reduce manufacturing times and costs, writes Ben Jordan of Altium, in the third of a three-part series. To meet these requirements, design teams have increasingly turned to 3D rigid-flex circuits to meet their project’s performance and production requirements. However, designing for flex or rigid-flex presents a number of challenges to electronic and mechanical design teams, that require careful consideration.
Ruminating Rigid-Flex – Flex Circuit Materials (Part 1)
Ruminating Rigid-Flex – Fab documentation (Part 2)
Ruminating Rigid-Flex – Dos and Don’ts of Flex Circuit Circuit Design (Part 3)
Leading up to now, we’ve looked at rigid-flex circuit materials, fabrication, and some aspects of design. In this last blog post, I want to show a handful of important rules to follow when routing copper for flex and rigid-flex circuits, that not only increase the fabrication yield but also the reliability and lifespan of the flex circuit.
It’s easy to look at the problems of layer stack design, parts placement, and cutouts and think we’ve got the issues down. But remember how flex circuits have some gnarly material quirks. Quirks ranging from relatively high z-axis expansion coefficients of adhesives, to the lower adhesion of copper to PI substrate and coverlay, to copper’s work hardening and fatigue. These can be compensated for largely by following some Dos and Don’ts.
This may seem obvious, but it’s worth saying. Decide just how much flex is needed up front. If your flex-circuit sections are only going to be folded during assembly and then left in a fixed position – such as in a handheld ultrasound device – then you are a lot freer in the number of layers, the type of copper (RA or ED) and so on you can use. On the other hand, if your flex-circuit sections are going to be continually moving, bending or rolling, then you should reduce the number of layers for each sub-stack of flex, and choose adhesive-less substrates.
Then, you can use the equations found in IPC-2223 (Eq. 1 for single-sided, Eq. 2 for double, etc.) to determine what is your minimum allowable bending radius for the flex section, based on your allowed deformation of copper and the characteristics of the other materials.
This example equation is for single-sided flex. You need to choose EB based on the target application, with 16% for single-crease installation of RA copper, 10% “flex-to-install” and 0.3% for “dynamic” flex designs (Source: IPC-2223B, 2008 http://www.ipc.org/TOC/IPC-2223B.pdf). Here, dynamic means continuous flex and roll during use of the product, such as a TFT panel connection on a mobile DVD player.
It is generally best to keep copper traces at right-angles to a flex-circuit bend. However there are some design situations where it’s unavoidable. In those cases keep the track work as gently curving as possible, and as the mechanical product design dictates, you could use conical radius bends.
Figure 4.1: Preferred bend locations. (click to expand)
Also referring to Figure 4.1 above, it’s best to avoid abrupt hard right-angle track work, and even better than using 45° hard corners, route the tracks with arc corner modes. This reduces stresses in the copper during bending.
Whenever you have a track entering a pad, particularly when there is an aligned row of them as in a flex-circuit terminator (shown below), this will form a weak spot where the copper will be fatigued over time. Unless there is going to be stiffener applied or a one-time crease, it’s advisable to taper down from the pads (hint: teardrop the pads and vias in the flex circuit!)
Figure 4.2: Trace width change and pad entries can cause weak spots. (click to expand)
Do Add Support for Pads
Copper on a flex circuit is more likely to detach from a polyimide substrate, due to the repeated stresses involved in bending as well as the lower adhesion (relative to FR-4). It is especially important therefore to provide support for exposed copper. Vias are inherently supported because the through-hole plating offers a suitable mechanical anchor from one flex layer to another. For this reason (as well as z-axis expansion) many fabricators will recommend additional through-hole plating of up to 1.5 mils for rigid-flex and flex circuits, over the conventional plating in rigid-only boards. Surface mount pads and non-plated-through pads are referred to as unsupported, and need additional measures to prevent detachment.
Figure 4.3: Supporting through-hole pads in flex with plating, anchoring stubs, and reduced coverlay access openings. (click to expand)
SMT component pads are among the most vulnerable, especially as the flex circuit may bend under the component’s rigid pin and solder fillet. Figures 4.4 and 4.5 show how using the coverlay “mask” openings to anchor pads one 2 sides will solve the problem. To do this while still allowing the right amount of solder the pads have to be somewhat larger than typical rigid-board footprints would have. This is compared in Figure 4.5, with the bottom SMD footprint used for flex mounted components. This obviously reduces the density of flex circuit component mounting, but by nature flex circuits cannot be very dense compared with rigid.
Figure 4.4: Coverlay openings for an SOW package showing anchoring at each end of each pad. (click to expand)
Figure 4.5: Adjusting the pad sizes and “mask” opening for coverlay. The top land pattern is for a nominal 0603 size chip component, whereas the bottom is modified for coverlay anchoring. (click to expand)
Figure 4.6: Size pads and coverlay openings to allow for adhesive squeeze out. (click to expand)
Referring to Figure 4.6, the second option is good for adhesive coverlay and the third for adhesive-less. Coverlays attached with adhesive will exhibit “squeeze out” of the adhesive, so the pad land and the access opening must be large enough to allow for this while providing a good solder fillet. IPC-2223 recommends 360° around the hole solder wetting for high reliability designs and 270° for reduced reliability flex designs.
For dynamic double-sided flex circuits, try to avoid laying traces over each other on the same direction (see Figure 4.7). Rather stagger them so the tensions are more evenly distributed between copper layers (see Figure 4.8).
Figure 4.7: Adjacent-layer copper traces are not recommended. (click to expand)
Figure 4.8: Staggered adjacent-layer traces are preferred. (click to expand)
Sometimes it’s necessary to carry a power or ground plane on a flex circuit. Using solid copper pours is okay, as long as you don’t mind significantly reduced flexibility, and possible buckling of the copper under tight-radius bends. Generally it’s best to use hatched polygons to retain a high level of flexibility.
A normal hatched polygon still has heavily biased copper stresses in 0°, 90°, and 45° angle directions, due to alignment of hatch traces and ‘X’s. A more statistically optimal hatch pattern would be hexagonal. This could be done using a negative plane layer and an array of hexagonal anti-pads, but it’s fast enough to build the hatch below ( Figure 4.9) with cut-and-paste.
Figure 4.9: Using hexagonal hatched polygons can spread the tension biases evenly among three angles. (click to expand)
This is by no means a complete set, but you should now have a few good tips on how to design flex circuits to give the best yield and highest reliability for the product – but be aware of the tradeoffs between cost, performance and reliability.
For multi-layer flex areas, it may sometimes be necessary to place vias to transition between layers. If possible it’s recommended not to place vias, as these can suffer fatigue rapidly in flexing movement. It is also necessary to keep at least 20 mils (about a ½ mm) clearance between the copper annulus of the nearest via to the rigid-to-flex board interface. Board edge clearance rules can take care of this automatically in the PCB CAD editor.
As for the need to place vias – if you must have vias in a flex circuit, use “rooms” to define regions where you know there will be no bends and use the PCB editor’s design rules to allow via placement only in those stationary areas. An alternative is to use the layer stack manager to define “rigid” sections that are ultimately flex but with a rigid dielectric stiffener material adhered to them.
Notice way back in Figure 3.1 how there are no hard corners, but rather there’s a minimum radius to each angle? IPC recommends greater radii than 1.5mm (about 60 mils), to reduce the risk of tearing of the flex circuit at corners. The same goes for slots and slits in the flex – make sure there’s a designed-in relief hole at each end of diameter 3mm (?”) or more. Another example of this is shown below.
Figure 4.10: Slots, slits and inside corners should have tear-relief holes or tangent curves with minimum 1.5mm radius. (click to expand)
The rule here, in essence, is that whenever you have an Inside corner (a flex-circuit edge corner with angle less than 180°, always use a tangential curved corner with radius greater than 1.5mm. If the corner is much less (more acute) than 90° then have a circular curve punched out of it, as shown in Figure 4.10.
In order to produce reliable rigid-flex based products, there are many considerations relating the fabrication and the end-use of the flex circuit, to the design of the copper pattern.
For more information you can download this free guidebook at http://go.altium.com/rigid-flex-pcb-design-guidebook.html
Ben Jordan got his start in electronics as an 8 year old, when his big brother got him his first soldering iron with a multivibrator LED flasher kit. Ben holds a Bachelor of Engineering with First Class Honors from the University of Southern Queensland, and has worked as an AE, FAE and in Marketing and management roles at Altium since 2004. Ben has more than 20 years experience designing electronics, PCBs, and embedded computing and FPGA hardware and software, and has research interests in signal processing, audio electronics, and PCB design.
Nice post with god examples and illustrations. Thanks for your post.
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The official website blog, highlighting new features, content, and initiatives. Written by the web editor of Electronics Weekly, Alun Williams.
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